`include "defines.v"
module id_ex(
	input wire clk,
	input wire rst,
	input wire[31:0] id_reg1,
	input wire[31:0] id_reg2,
	input wire[4:0] id_reg3_addr,
	input wire id_reg3_write,
	input wire[`AluOpWidth-1:0] id_alu_op,
	// input wire[`AluSelWidth-1:0] id_alu_sel,
	input wire[5:0] pause, //流水线暂停信号
	output reg[31:0] ex_reg1,
	output reg[31:0] ex_reg2,
	output reg[4:0] ex_reg3_addr,
	output reg ex_reg3_write,
	output reg[`AluOpWidth-1:0] ex_alu_op,
	// output reg[`AluSelWidth-1:0] ex_alu_sel
	//延迟槽相关信号
	input wire id_is_in_delaySlot_i, //当前译码阶段的指令是否是延迟槽指令
	input wire id_next_inst_is_in_delaySlot, //下一条进入译码阶段的指令是否是延迟槽指令
	input wire[31:0] id_link_addr, //返回地址
	
	output reg ex_is_in_delaySlot, //当前执行阶段的指令是否是延迟槽指令
	output reg id_is_in_delaySlot_o, //当前译码阶段的指令是否是延迟槽指令
	output reg[31:0] ex_link_addr, //返回地址
	
	input wire[31:0] id_inst,
	output reg[31:0] ex_inst
);
	
	always@(posedge clk) 
		if(rst == `RstEnable)
		begin
			ex_reg1 <= `ZeroWord;
			ex_reg2 <= `ZeroWord;
			ex_reg3_addr <= 5'b00000;
			ex_reg3_write <= `WriteDisable;
			ex_alu_op <= `ALU_NOP_OP;
			// ex_alu_sel <= `ALU_RES_NOP;
			ex_is_in_delaySlot <= `NotInDelaySlot;
			id_is_in_delaySlot_o <= `NotInDelaySlot;
			ex_link_addr <= `ZeroWord;
			ex_inst <= `ZeroWord;
		end
		else if(pause[2] == `PAUSE && pause[3] == `NO_PAUSE) //译码阶段暂停，执行阶段继续
		begin
			ex_reg1 <= `ZeroWord;
			ex_reg2 <= `ZeroWord;
			ex_reg3_addr <= 5'b00000;
			ex_reg3_write <= `WriteDisable;
			ex_alu_op <= `ALU_NOP_OP;
			
			ex_is_in_delaySlot <= `NotInDelaySlot;
			ex_link_addr <= `ZeroWord;
			
			ex_inst <= `ZeroWord;
		end
		else if(pause[2] == `NO_PAUSE)
		begin
			ex_reg1 <= id_reg1;
			ex_reg2 <= id_reg2;
			ex_reg3_addr <= id_reg3_addr;
			ex_reg3_write <= id_reg3_write;
			ex_alu_op <= id_alu_op;
			// ex_alu_sel <= id_alu_sel;
			ex_is_in_delaySlot <= id_is_in_delaySlot_i;
			id_is_in_delaySlot_o <= id_next_inst_is_in_delaySlot;
			ex_link_addr <= id_link_addr;
			
			ex_inst <= id_inst;
		end
endmodule